device:02
Index of /FSS-BCZ/root/sys/dev/char/226:0/device/subsystem/drivers/pci1xxxx serial
Index of /FSS-BCZ/root/sys/dev/char/226:0/device/subsystem/drivers/pci1xxxx serial
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O4/_I|+ ? /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
/* QLogic qed NIC Driver
* Copyright (c) 2015 QLogic Corporation
* Copyright (c) 2019-2020 Marvell International Ltd.
*/
#ifndef __FCOE_COMMON__
#define __FCOE_COMMON__
/*********************/
/* FCOE FW CONSTANTS */
/*********************/
#define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12
/* The fcoe storm task context protection-information of Ystorm */
struct protection_info_ctx {
__le16 flags;
#define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
#define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0
#define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1
#define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2
#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1
#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF
#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
#define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F
#define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9
u8 dix_block_size;
u8 dst_size;
};
/* The fcoe storm task context protection-information of Ystorm */
union protection_info_union_ctx {
struct protection_info_ctx info;
__le32 value;
};
/* FCP CMD payload */
struct fcoe_fcp_cmd_payload {
__le32 opaque[8];
};
/* FCP RSP payload */
struct fcoe_fcp_rsp_payload {
__le32 opaque[6];
};
/* FCP RSP payload */
struct fcp_rsp_payload_padded {
struct fcoe_fcp_rsp_payload rsp_payload;
__le32 reserved[2];
};
/* FCP RSP payload */
struct fcoe_fcp_xfer_payload {
__le32 opaque[3];
};
/* FCP RSP payload */
struct fcp_xfer_payload_padded {
struct fcoe_fcp_xfer_payload xfer_payload;
__le32 reserved[5];
};
/* Task params */
struct fcoe_tx_data_params {
__le32 data_offset;
__le32 offset_in_io;
u8 flags;
#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1
#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0
#define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1
#define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1
#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1
#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2
#define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F
#define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
u8 dif_residual;
__le16 seq_c