input:b0019v0000p0001e0000-e0,1,k74,8F,ramlsfw *lY>TD  r`S 5_I|+  M T/* SPDX-License-Identifier: GPL-2.0 */ /* Atomic operations usable in machine independent code */ #ifndef _LINUX_ATOMIC_H #define _LINUX_ATOMIC_H #include #include #include /* * Relaxed variants of xchg, cmpxchg and some atomic operations. * * We support four variants: * * - Fully ordered: The default implementation, no suffix required. * - Acquire: Provides ACQUIRE semantics, _acquire suffix. * - Release: Provides RELEASE semantics, _release suffix. * - Relaxed: No ordering guarantees, _relaxed suffix. * * For compound atomics performing both a load and a store, ACQUIRE * semantics apply only to the load and RELEASE semantics only to the * store portion of the operation. Note that a failed cmpxchg_acquire * does -not- imply any memory ordering constraints. * * See Documentation/memory-barriers.txt for ACQUIRE/RELEASE definitions. */ #define atomic_cond_read_acquire(v, c) smp_cond_load_acquire(&(v)->counter, (c)) #define atomic_cond_read_relaxed(v, c) smp_cond_load_relaxed(&(v)->counter, (c)) #define atomic64_cond_read_acquire(v, c) smp_cond_load_acquire(&(v)->counter, (c)) #define atomic64_cond_read_relaxed(v, c) smp_cond_load_relaxed(&(v)->counter, (c)) /* * The idea here is to build acquire/release variants by adding explicit * barriers on top of the relaxed variant. In the case where the relaxed * variant is already fully ordered, no additional barriers are needed. * * If an architecture overrides __atomic_acquire_fence() it will probably * want to define smp_mb__after_spinlock(). */ #ifndef __atomic_acquire_fence #define __atomic_acquire_fence smp_mb__after_atomic #endif #ifndef __atomic_release_fence #define __atomic_release_fence smp_mb__before_atomic #endif #ifndef __atomic_pre_full_fence #define __atomic_pre_full_fence smp_mb__before_atomic #endif #ifndef __atomic_post_full_fence #define __atomic_post_full_fence smp_mb__after_atomic #endif #define __atomic_op_acquire(op, args...) \ ({ \ typeof(op##_relaxed(args)) __ret = op##_relaxed(args); \ __atomic_acquire_fence(); \ __ret; \ }) #define __atomic_op_release(op, args...) \ ({ \ __atomic_release_fence(); \ op##_relaxed(args); \ }) #define __atomic_op_fence(op, args...) \ ({ \ typeof(op##_relaxed(args)) __ret; \ __atomic_pre_full_fence(); \ __ret = op##_relaxed(args); \ __atomic_post_full_fence(); \ __ret; \ }) #include #include #include #endif /* _LINUX_ATOMIC_H */ /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __LINUX_LOCKREF_H #define __LINUX_LOCKREF_H /* * Locked reference counts. * * These are different from just plain atomic refcounts in that they * are atomic with respect to the spinlock that goes with them. In * particular, there can be implementations that don't actually get * the spinlock for the common decrement/increment operations, but they * still have to check that the operation is done semantically as if * the spinlock had been taken (using a cmpxchg operation that covers * both the lock and the count word, or using memory transactions, for * example). */ #include #include #define USE_CMPXCHG_LOCKREF \ (IS_ENABLED(CONFIG_ARCH_USE_CMPXCHG_LOCKREF) && \ IS_ENABLED(CONFIG_SMP) && SPINLOCK_SIZE <= 4) struct lockref { union { #if USE_CMPXCHG_LOCKREF aligned_u64 lock_count; #endif struct { spinlock_t lock; int count; }; }; }; extern void lockref_get(struct lockref *); extern int lockref_put_return(struct lockref *); extern int lockref_get_not_zero(struct lockref *); extern int lockref_put_or_lock(struct lockref *); extern void lockref_mark_dead(struct lockref *); extern int lockref_get_not_dead(struct lockref *); /* Must be called under spinlock for reliable results */ st