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 { Index of /FSS-BCZ/root/sys/dev/char/242:0/device/input/input5/js0

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*lY>TD  r`S _I|+ /* SPDX-License-Identifier: GPL-2.0-only */ /* Copyright (C) 2024 Intel Corporation */ #ifndef __LIBETH_CACHE_H #define __LIBETH_CACHE_H #include /** * libeth_cacheline_group_assert - make sure cacheline group size is expected * @type: type of the structure containing the group * @grp: group name inside the struct * @sz: expected group size */ #if defined(CONFIG_64BIT) && SMP_CACHE_BYTES == 64 #define libeth_cacheline_group_assert(type, grp, sz) \ static_assert(offsetof(type, __cacheline_group_end__##grp) - \ offsetofend(type, __cacheline_group_begin__##grp) == \ (sz)) #define __libeth_cacheline_struct_assert(type, sz) \ static_assert(sizeof(type) == (sz)) #else /* !CONFIG_64BIT || SMP_CACHE_BYTES != 64 */ #define libeth_cacheline_group_assert(type, grp, sz) \ static_assert(offsetof(type, __cacheline_group_end__##grp) - \ offsetofend(type, __cacheline_group_begin__##grp) <= \ (sz)) #define __libeth_cacheline_struct_assert(type, sz) \ static_assert(sizeof(type) <= (sz)) #endif /* !CONFIG_64BIT || SMP_CACHE_BYTES != 64 */ #define __libeth_cls1(sz1) SMP_CACHE_ALIGN(sz1) #define __libeth_cls2(sz1, sz2) (SMP_CACHE_ALIGN(sz1) + SMP_CACHE_ALIGN(sz2)) #define __libeth_cls3(sz1, sz2, sz3) \ (SMP_CACHE_ALIGN(sz1) + SMP_CACHE_ALIGN(sz2) + SMP_CACHE_ALIGN(sz3)) #define __libeth_cls(...)