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IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef KFD_IOCTL_H_INCLUDED #define KFD_IOCTL_H_INCLUDED #include #include /* * - 1.1 - initial version * - 1.3 - Add SMI events support * - 1.4 - Indicate new SRAM EDC bit in device properties * - 1.5 - Add SVM API * - 1.6 - Query clear flags in SVM get_attr API * - 1.7 - Checkpoint Restore (CRIU) API * - 1.8 - CRIU - Support for SDMA transfers with GTT BOs * - 1.9 - Add available memory ioctl * - 1.10 - Add SMI profiler event log * - 1.11 - Add unified memory for ctx save/restore area * - 1.12 - Add DMA buf export ioctl * - 1.13 - Add debugger API * - 1.14 - Update kfd_event_data * - 1.15 - Enable managing mappings in compute VMs with GEM_VA ioctl * - 1.16 - Add contiguous VRAM allocation flag * - 1.17 - Add SDMA queue creation with target SDMA engine ID * - 1.18 - Rename pad in set_memory_policy_args to misc_process_flag */ #define KFD_IOCTL_MAJOR_VERSION 1 #define KFD_IOCTL_MINOR_VERSION 18 struct kfd_ioctl_get_version_args { __u32 major_version; /* from KFD */ __u32 minor_version; /* from KFD */ }; /* For kfd_ioctl_create_queue_args.queue_type. */ #define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0 #define KFD_IOC_QUEUE_TYPE_SDMA 0x1 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 #define KFD_IOC_QUEUE_TYPE_SDMA_BY_ENG_ID 0x4 #define KFD_MAX_QUEUE_PERCENTAGE 100 #define KFD_MAX_QUEUE_PRIORITY 15 #define KFD_MIN_QUEUE_RING_SIZE 1024 struct kfd_ioctl_create_queue_args { __u64 ring_base_address; /* to KFD */ __u64 write_pointer_address; /* to KFD */ __u64 read_pointer_address; /* to KFD */ __u64 doorbell_offset; /* from KFD */ __u32 ring_size; /* to KFD */ __u32 gpu_id; /* to KFD */ __u32 queue_type; /* to KFD */ __u32 queue_percentage; /* to KFD */ __u32 queue_priority; /* to KFD */ __u32 queue_id; /* from KFD */ __u64 eop_buffer_address; /* to KFD */ __u64 eop_buffer_size; /* to KFD */ __u64 ctx_save_restore_address; /* to KFD */ __u32 ctx_save_restore_size; /* to KFD */ __u32 ctl_stack_size; /* to KFD */ __u32 sdma_engine_id; /* to KFD */ __u32 pad; }; struct kfd_ioctl_destroy_queue_args { __u32 queue_id; /* to KFD */ __u32 pad; }; struct kfd_ioctl_update_queue_args { __u64 ring_base_address; /* to KFD */ __u32 queue_id; /* to KFD */ __u32 ring_size; /* to KFD */ __u32 queue_percentage; /* to KFD */ __u32 queue_priority; /* to KFD */ }; struct kfd_ioctl_set_cu_mask_args { __u32 queue_id; /* to KFD */ __u32 num_cu_mask; /* to KFD */ __u64 cu_mask_ptr; /* to KFD */ }; struct kfd_ioctl_get_queue_wave_state_args { __u64 ctl_stack_address; /* to KFD */ __u32 ctl_stack_used_size; /* from KFD */ __u32 save_area_used_size; /* from KFD */ __u32 queue_id; /* to KFD */ __u32 pad; }; struct kfd_ioctl_get_available_memory_args { __u64 available; /* from KFD */ __u32 gpu_id; /* to KFD */ __u32 pad; }; struct kfd_dbg_device_info_entry { __u64 exception_status; __u64 lds_base; __u64 lds_limit; __u64 scratch_base; __u64 scratch_limit; __u64 gpuvm_base; __u64 gpuvm_limit; __u32 gpu_id; __u32 location_id; __u32 vendor_id; __u32 device_id; __u32 revision_id; __u32 subsystem_vendor_id; __u32 subsystem_device_id; __u32 fw_version; __u32 gfx_target_version; __u32 simd_count; __u32 max_waves_per_simd; __u32 array_count; __u32 simd_arrays_per_engine; __u32 num_xcc; __u32 capability; __u32 debug_prop; }; /* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */ #define KFD_IOC_CACHE_POLICY_COHERENT 0 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 /* Misc. per process flags */ #define KFD_PROC_FLAG_MFMA_HIGH_PRECISION (1 << 0) struct kfd_ioctl_set_memory_policy_args { __u64 alternate_aperture_base; /* to KFD */ __u64 alternate_aperture_size; /* to KFD */ _