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#!ˆl–ßi~”Jj"TÊ�ÆÞ¸ÓêbÑ¿Í 147̿ʓ![Unit] Description=p11-kit server [Socket] Priority=6 Backlog=5 ListenStream=%t/p11-kit/pkcs11 SocketMode=0600 [Install] WantedBy=sockets.target #ˆÀÍ 648̿ʈ#/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* atm_eni.h - Driver-specific declarations of the ENI driver (for use by driver-specific utilities) */ /* Written 1995-2000 by Werner Almesberger, EPFL LRC/ICA */ #ifndef LINUX_ATM_ENI_H #define LINUX_ATM_ENI_H #include struct eni_multipliers { int tx,rx; /* values are in percent and must be > 100 */ }; #define ENI_MEMDUMP _IOW('a',ATMIOC_SARPRV,struct atmif_sioc) /* printk memory map */ #define ENI_SETMULT _IOW('a',ATMIOC_SARPRV+7,struct atmif_sioc) /* set buffer multipliers */ #endif %ˆÀÍ ƒyÑ=Ì¿Ê"%/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ /* * Header File for FPGA DFL User API * * Copyright (C) 2017-2018 Intel Corporation, Inc. * * Authors: * Kang Luwei * Zhang Yi * Wu Hao * Xiao Guangrong */ #ifndef _LINUX_FPGA_DFL_H #define _LINUX_FPGA_DFL_H #include #include #define DFL_FPGA_API_VERSION 0 /* * The IOCTL interface for DFL based FPGA is designed for extensibility by * embedding the structure length (argsz) and flags into structures passed * between kernel and userspace. This design referenced the VFIO IOCTL * interface (include/uapi/linux/vfio.h). */ #define DFL_FPGA_MAGIC 0xB6 #define DFL_FPGA_BASE 0 #define DFL_PORT_BASE 0x40 #define DFL_FME_BASE 0x80 /* Common IOCTLs for both FME and AFU file descriptor */ /** * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) * * Report the version of the driver API. * Return: Driver API Version. */ #define DFL_FPGA_GET_API_VERSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0) /** * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) * * Check whether an extension is supported. * Return: 0 if not supported, otherwise the extension is supported. */ #define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1) /* IOCTLs for AFU file descriptor */ /** * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0) * * Reset the FPGA Port and its AFU. No parameters are supported. * Userspace can do Port reset at any time, e.g. during DMA or PR. But * it should never cause any system level issue, only functi