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eſ ? '/* SPDX-License-Identifier: GPL-2.0 */
/*
* CPPI5 descriptors interface
*
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
*/
#ifndef __TI_CPPI5_H__
#define __TI_CPPI5_H__
#include
#include
#include
/**
* struct cppi5_desc_hdr_t - Descriptor header, present in all types of
* descriptors
* @pkt_info0: Packet info word 0 (n/a in Buffer desc)
* @pkt_info0: Packet info word 1 (n/a in Buffer desc)
* @pkt_info0: Packet info word 2 (n/a in Buffer desc)
* @src_dst_tag: Packet info word 3 (n/a in Buffer desc)
*/
struct cppi5_desc_hdr_t {
u32 pkt_info0;
u32 pkt_info1;
u32 pkt_info2;
u32 src_dst_tag;
} __packed;
/**
* struct cppi5_host_desc_t - Host-mode packet and buffer descriptor definition
* @hdr: Descriptor header
* @next_desc: word 4/5: Linking word
* @buf_ptr: word 6/7: Buffer pointer
* @buf_info1: word 8: Buffer valid data length
* @org_buf_len: word 9: Original buffer length
* @org_buf_ptr: word 10/11: Original buffer pointer
* @epib[0]: Extended Packet Info Data (optional, 4 words), and/or
* Protocol Specific Data (optional, 0-128 bytes in
* multiples of 4), and/or
* Other Software Data (0-N bytes, optional)
*/
struct cppi5_host_desc_t {
struct cppi5_desc_hdr_t hdr;
u64 next_desc;
u64 buf_ptr;
u32 buf_info1;
u32 org_buf_len;
u64 org_buf_ptr;
u32 epib[];
} __packed;
#define CPPI5_DESC_MIN_ALIGN (16U)
#define CPPI5_INFO0_HDESC_EPIB_SIZE (16U)
#define CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE (128U)
#define CPPI5_INFO0_HDESC_TYPE_SHIFT (30U)
#define CPPI5_INFO0_HDESC_TYPE_MASK GENMASK(31, 30)
#define CPPI5_INFO0_DESC_TYPE_VAL_HOST (1U)
#define CPPI5_INFO0_DESC_TYPE_VAL_MONO (2U)
#define CPPI5_INFO0_DESC_TYPE_VAL_TR (3U)
#define CPPI5_INFO0_HDESC_EPIB_PRESENT BIT(29)
/*
* Protocol Specific Words location:
* 0 - located in the descriptor,
* 1 = located in the SOP Buffer immediately prior to the data.
*/
#define CPPI5_INFO0_HDESC_PSINFO_LOCATION BIT(28)
#define CPPI5_INFO0_HDESC_PSINFO_SIZE_SHIFT (22U)
#define CPPI5_INFO0_HDESC_PSINFO_SIZE_MASK GENMASK(27, 22)
#define CPPI5_INFO0_HDESC_PKTLEN_SHIFT (0)
#define CPPI5_INFO0_HDESC_PKTLEN_MASK GENMASK(21, 0)
#define CPPI5_INFO1_DESC_PKTERROR_SHIFT (28U)
#define CPPI5_INFO1_DESC_PKTERROR_MASK GENMASK(31, 28)
#define CPPI5_INFO1_HDESC_PSFLGS_SHIFT (24U)
#define CPPI5_INFO1_HDESC_PSFLGS_MASK GENMASK(27, 24)
#define CPPI5_INFO1_DESC_PKTID_SHIFT (14U)
#define CPPI5_INFO1_DESC_PKTID_MASK GENMASK(23, 14)
#define CPPI5_INFO1_DESC_FLOWID_SHIFT (0)
#define CPPI5_INFO1_DESC_FLOWID_MASK GENMASK(13, 0)
#define CPPI5_INFO1_DESC_FLOWID_DEFAULT CPPI5_INFO1_DESC_FLOWID_MASK
#define CPPI5_INFO2_HDESC_PKTTYPE_SHIFT (27U)
#define CPPI5_INFO2_HDESC_PKTTYPE_MASK GENMASK(31, 27)
/* Return Policy: 0 - Entire packet 1 - Each buffer */
#define CPPI5_INFO2_HDESC_RETPOLICY BIT(18)
/*
* Early Return:
* 0 = desc pointers should be returned after all reads have been completed
* 1 = desc pointers should be returned immediately upon fetching
* the descriptor and beginning to transfer data.
*/
#define CPPI5_INFO2_HDESC_EARLYRET BIT(17)
/*
* Return Push Po